Field of the Invention
The present invention relates to a multiprocessor system having a plurality of processors and a common memory used in common by the processors, and more particularly to a method of two-way communication in a multiprocessor system for mutually exchanging messages among processors through a common memory.
Description of the Related Art
FIG. 9 is a diagram schematically illustrating an example of a multiprocessor system. In the drawing, a plurality of processors 112 and a main common memory 113 are connected to a system bus 111, and each of the processors 112 has a central processor (CPU) 114 and a local memory 115. The main common memory 113 is used in common by the processors 112, and is accessed by the processors 112 via the system bus 111.
FIG. 10 is a diagram schematically illustrating another example of the multiprocessor system, in which each of the processors 112 is provided with a sub common memory 116. In this case, since each of the processors 112 is capable of accessing its own sub common memory 116 without via the system bus 111, high-speed processing becomes possible. It goes without saying that each of the processors 112 is capable of accessing the main common memory 113 via the system bus 111 and mutually accessing the sub common memory 116 belonging to another processor 112.
Here, if a comparison is made between the multiprocessor systems of the above-described two examples, although there is a difference in that in the latter example each of the processors 112 has the sub common memory 116 assigned thereto, the logical configurations of the two examples are equivalent since each of the sub common memories 116 is accessed by each processor 112 in the same way as the main common memory 113 is accessed.
When communication is effected between two processors in such a multiprocessor system, a common memory is used.
For example, when data communication is effected from a first processor 121 to a second processor 122, as shown in FIG. 11, the first processor 121 writes data to be communicated into a buffer 124 located in a common memory 123, and sets a flag 125 in the common memory 123 so as to indicate that the data has been written into the buffer 124. When the flag 125 is set, the second processor 122 reads the data from the buffer 124 and resets the flag 125. Accordingly, each time the data is transmitted from the first processor 121 to the second processor 122, the setting and resetting of the flag 125 are repeated. However, in the case where data communication between processors is effected by using the flag in the above-described manner, both processors must periodically monitor the flag in the common memory, so that the efficiency is poor.
Accordingly, there is an alternative method in which an interruption is generated instead of using the flag. In other words, when the first processor writes data into the buffer, an interruption from the first processor to the second processor is generated, and the second processor reads the data from the buffer in response to this interruption. However, since an interruption must be generated each time data is transmitted, the efficiency is not improved by a substantial degree.
Thus, in a conventional multiprocessor system, each time communication is effected wherein one of two processors writes data into the buffer located in the common memory and the other reads the data from the buffer, it is necessary to either set/reset the flag or generate an interruption. For this reason, there has been a problem in that data communication cannot be effected with high efficiency.
In addition, if an attempt is made to conduct data communication reciprocally among a plurality of processors by using the above-described data communication system, it has been difficult to systematically manage the two-way communication since data communication is independent for each one-way communication between two processors.